Title :
A Reference-Less Single-Loop Half-Rate Binary CDR
Author :
Jalali, Mohammad Sadegh ; Sheikholeslami, Ali ; Kibune, Masaya ; Tamura, Hirotaka
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper proposes a half-rate single-loop reference-less binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu´s 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6 × when it is activated.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; phase detectors; voltage-controlled oscillators; CDR phase error; Fujitsu CMOS; VCO clock; bit rate 10 Gbit/s; bit rate 12.1 Gbit/s; bit rate 8.5 Gbit/s; clock and data recovery; frequency detection; half-rate binary CDR; phase detector; power 11 mW; reference-less binary CDR; single-loop binary CDR; size 65 nm; Clocks; Delay lines; Delays; Detectors; Phase frequency detector; Switches; Voltage-controlled oscillators; Burst-mode CDR; clock and data recovery; cycle-slipping; frequency detection; gated VCO;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2429714
