DocumentCode :
743143
Title :
Secure Systolic Montgomery Modular Multiplier Over Prime Fields Resilient to Fault-Injection Attacks
Author :
Qi Yang ; Xiaoting Hu ; Zhongping Qin
Author_Institution :
Sch. of Comput. Sci., Wuhan Univ., Wuhan, China
Volume :
23
Issue :
9
fYear :
2015
Firstpage :
1889
Lastpage :
1902
Abstract :
This paper focuses on the security architecture for Montgomery modular multiplication over prime fields (MMMopfs). We propose a class of noninterleaved systolic secure architectures for MMMopf. Each of the proposed secure architectures has two modules, in which one is a main function module (MFM) which computes MMMopf, the other is an error detection module (EDM) which detects faults either owing to natural causes or deliberate fault injection by an attacker. In our secure architectures, several computing types of systolic array structures are adopted to implement the MFMs, and two error-detecting styles based on linear arithmetic codes are employed to construct the EDMs. We explore various combinations of computing types and error-detecting styles to get some excellent secure architectures. The best implementation of our secure architecture of Style-I can detect 99.9985% of faults in processing elements (PEs), with an average delay of 8.56% of whole Montgomery modular multiplication (MMM) computing time, and about 26.73% overhead resources. Meanwhile, the throughput rate of its MFM is 34.44% higher than that of the best pure MMMopf implementation in literature, with almost the same hardware consumption. The error detection capability, overhead proportion, and the average error-reporting delay of our secure architectures are comparable with or better than Hariri and Reyhani-Masoleh´s work on secure MMM over binary extension fields. Moreover, our secure architecture of Style-II can localize 90.63% of injected PEs faults, on condition that the number of affected PEs does not exceed 3. The property of our secure architectures that the injected faults could be localized and detected is novel and valuable.
Keywords :
arithmetic codes; error detection; linear codes; multiplying circuits; systolic arrays; error detection module; error-detecting styles; error-reporting delay; fault injection attacks; hardware consumption; linear arithmetic codes; main function module; noninterleaved systolic secure architectures; overhead proportion; prime fields; secure systolic Montgomery modular multiplier; systolic array structures; Arrays; Delays; Hardware; Prediction algorithms; Registers; Throughput; Concurrent error detection; Montgomery modular multiplication (MMM); systolic array;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2356015
Filename :
6909065
Link To Document :
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