Oscillation-Based Prebond TSV Test

Author

Li-Ren Huang ; Shi-Yu Huang ; Sunter, Sedat ; Kun-Han Tsai ; Wu-Tung Cheng

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

32

Issue

9

fYear

2013

Firstpage

1440

Lastpage

1444

Abstract

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Keywords

circuit oscillations; design for testability; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; design-for-testability circuit; known-good-die test; leakage fault; oscillation-based prebond TSV test; prebond through-silicon vias quality testing; resistive open fault; still-thick wafer; test structure; versatile prebond TSV test method; Capacitance; Circuit faults; Fault detection; Fault location; Integrated circuit modeling; Resistance; Through-silicon vias; 3-D integrated circuit (IC); Design-for-Testability (DfT); Known-Good-Die (KGD); leakage fault; prebond; resistive open fault; through-silicon vias (TSV);

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2013.2259626

Filename

6582613