Title :
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies
Author :
Lee, Jri ; Ping-Chuan Chiang ; Pen-Jui Peng ; Li-Yang Chen ; Chih-Chi Weng
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; decision feedback equalisers; mixed analogue-digital integrated circuits; phase locked loops; transceivers; CDR; CMOS technology; CTLE; DFE; FFE; MUX; NRZ RX; NRZ TX; PAM4 RX; PAM4 SerDes transceivers; PAM4 TX; built-in PLL; clock and data recovery; decision-feedback equalizer; feed-forward equalizer; phase aligner; phase-locked loops; serializer-deserializer; Bandwidth; Clocks; Decision feedback equalizers; Optical signal processing; Phase locked loops; Signal to noise ratio; Transceivers; Clock and data recovery (CDR); NRZ; PAM4; SerDes; equalizer; high-speed serial link; phase-locked loop (PLL); transceiver (TRX);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2433269
