Title :
Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits
Author :
El-Maleh, Aiman H. ; Daud, Khaled A. K.
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit.
Keywords :
combinational circuits; cosmic rays; masks; probability; radiation hardening (electronics); radioactive decay schemes; MCNC combinational benchmarks; circuit failure reduction probability; combinational logic circuits; cosmic rays; digital system design; fast extraction algorithm; fault masking; logical masking; multilevel circuit; radiation-induced particle; radioactivity decay; soft error masking; soft error probability; soft error tolerant combinational circuits; subcircuit extracting; Circuit faults; Combinational circuits; Fault tolerance; Fault tolerant systems; Integrated circuit reliability; Logic gates; Wires; Combinational circuit reliability; fault tolerance; single event transient; single event upset; soft errors;
Journal_Title :
Reliability, IEEE Transactions on
DOI :
10.1109/TR.2015.2440234