DocumentCode :
744015
Title :
Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips
Author :
Tosun, Suleyman ; Ajabshir, Vahid B. ; Mercanoglu, Ozge ; Ozturk, Ozcan
Author_Institution :
Dept. of Comput. Eng., Hacettepe Univ., Ankara, Turkey
Volume :
34
Issue :
9
fYear :
2015
Firstpage :
1495
Lastpage :
1508
Abstract :
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
Keywords :
application specific integrated circuits; fault tolerance; network routing; network topology; network-on-chip; NoC communication; NoC topology; application-specific network-on-chips; fault-tolerant topology generation method; routing path; simulated annealing-based application mapping algorithm; Energy consumption; Fault tolerance; Fault tolerant systems; Network topology; Ports (Computers); Routing; Topology; Energy minimization; Network-on-Chip; energy minimization; fault tolerance; mapping; network-on-chip (NoC); topology design;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2015.2413848
Filename :
7061387
Link To Document :
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