A 40-Gb/s 310-fJ/b Inverter-Based CMOS Optical Receiver Front-End

Author

Kangyeob Park ; Won-Seok Oh

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

27

Issue

18

fYear

2015

Firstpage

1931

Lastpage

1933

Abstract

This letter presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. Using an inverter-based topology for both the transimpedance amplifier and the post amplifier, high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpedance combinations are utilized to acquire a bandwidth of 29.6 GHz. A low-dropout voltage regulator is applied to reduce the supply noise of the single-ended amplifiers. The prototype chip excluding output buffer consumes only 12.4 mW (310 fJ/b) at a 1.2 V single supply, and the integrated input referred noise is 9.2 μA_rms.

Keywords

CMOS integrated circuits; invertors; operational amplifiers; optical receivers; voltage regulators; CMOS technology; bandwidth 29.6 GHz; bit rate 40 Gbit/s; cascaded amplifiers; energy efficiency; integrated input referred noise; inverter-based CMOS optical receiver front-end; inverter-based topology; low-dropout voltage regulator; output buffer; post amplifier; power 12.4 mW; prototype chip; single-ended amplifiers; transconductance; transimpedance amplifier; voltage 1.2 V; Bandwidth; Integrated optics; Optical amplifiers; Optical fibers; Optical receivers; CMOS; Inverter-based shunt-feedback; inverter-based shunt-feedback; optical receiver; post amplifier (PA); transimpedance amplifier (TIA);

fLanguage

English

Journal_Title

Photonics Technology Letters, IEEE

Publisher

ieee

ISSN

1041-1135

Type

jour

DOI

10.1109/LPT.2015.2447283

Filename

7128343