DocumentCode :
744177
Title :
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes
Author :
Davoodi, Azadeh ; Hu, Jiang ; Ozdal, Mustafa ; Sze, Cliff C. N.
Author_Institution :
Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA
Volume :
34
Issue :
4
fYear :
2015
fDate :
4/1/2015 12:00:00 AM
Firstpage :
501
Lastpage :
501
Abstract :
Advanced technology nodes have engendered new challenges in the design of integrated circuits (ICs), which can only be addressed through innovations in physical design techniques and algorithms. These challenges stem from factors such as increasingly complex manufacturing design rules, cell pin access in technologies utilizing multiple patterning and FinFETs, various types of restrictions and blockages on the routing layers, and complexity of the physical floorplan, for example due to irregular shapes of placeable areas. This issue and the next issue feature the special section on physical design aimed at addressing these challenges.
Keywords :
Algorithm design and analysis; Design methodology; FinFETs; Integrated circuit synthesis; Network architecture; Special issues and sections; Through-silicon vias;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2015.2410671
Filename :
7062064
Link To Document :
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