• DocumentCode
    744675
  • Title

    Competitive learning with floating-gate circuits

  • Author

    Hsu, David ; Figueroa, Miguel ; Diorio, Chris

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
  • Volume
    13
  • Issue
    3
  • fYear
    2002
  • fDate
    5/1/2002 12:00:00 AM
  • Firstpage
    732
  • Lastpage
    744
  • Abstract
    Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-μm CMOS process
  • Keywords
    integrated logic circuits; neural chips; neural net architecture; neural nets; unsupervised learning; VLSI; automaximizing bump circuit; classification; clustering; competitive learning; competitive-learning networks; floating-gate circuits; CMOS process; Circuit simulation; Clustering algorithms; Computer architecture; Computer science; Data analysis; Neurons; Physics computing; Silicon; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Neural Networks, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1045-9227
  • Type

    jour

  • DOI
    10.1109/TNN.2002.1000139
  • Filename
    1000139