Low-cost low-power HV startup circuit with 50 V pJFET and 700 V T-nJFET

Author

Kun Mao ; Ming Qiao ; Zhaoji Li ; Bo Zhang

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

49

Issue

21

fYear

2013

fDate

October 10 2013

Firstpage

1318

Lastpage

1320

Abstract

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional technology, a mass of module area is saved. This mainly benefits from: first, with increase of V_DS, I_OFF (leakage current in off-state) can be quickly pinched off to a low value by pJFET without a large layout area which is needed for the traditional resistance method. Secondly, T-nJFET is located at the drain terminal of T-nLDMOS (triple RESURF LDMOS) with common drain electrode which also saves large area than traditional independent nJFET. Moreover, pJFET brings stable and low I_OFF which leads to 4 mW P_OFF (static power consumption in off-state) due to its low V_P (pinch-off voltage) and high BV_DS.

Keywords

JFET integrated circuits; integrated circuit layout; junction gate field effect transistors; low-power electronics; power field effect transistors; T-nJFET; T-nLDMOS; drain electrode; drain terminal; high-voltage startup circuit; leakage current; low-cost low-power HV startup circuit; off-state; pJFET; pinch-off voltage; power 4 mW; static power consumption; triple-resurf LDMOS; triple-resurf nJFET; voltage 50 V; voltage 700 V;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2013.2459

Filename

6651353