Low-cost low-power HV startup circuit with 50 V pJFET and 700 V T-nJFET

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional technology, a mass of module area is saved. This mainly benefits from: first, with increase of V_DS, I_OFF (leakage current in off-state) can be quickly pinched off to a low value by pJFET without a large layout area which is needed for the traditional resistance method. Secondly, T-nJFET is located at the drain terminal of T-nLDMOS (triple RESURF LDMOS) with common drain electrode which also saves large area than traditional independent nJFET. Moreover, pJFET brings stable and low I_OFF which leads to 4 mW P_OFF (static power consumption in off-state) due to its low V_P (pinch-off voltage) and high BV_DS.