How to avoid false lock in SPLL frequency synthesizers

Two attractors coexist in sampling phase-locked loop (SPLL) implemented with a loop filter if the time constant of the loop filter is much larger than the reference period. Consequently, after acquisition, the SPLL either reaches the desired phase lock or gets into false lock, depending on the initial conditions. This paper develops a model for false lock which explains why the SPLL may get into false lock. Having understood its mechanism, a simple circuit is proposed to prevent the development of false lock.