• DocumentCode
    745054
  • Title

    Weighted pseudorandom hybrid BIST

  • Author

    Jas, Abhijit ; Krishna, C.V. ; Touba, Nur A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Intel Corp., Austin, TX, USA
  • Volume
    12
  • Issue
    12
  • fYear
    2004
  • Firstpage
    1277
  • Lastpage
    1283
  • Abstract
    This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.
  • Keywords
    built-in self test; data compression; random number generation; built in self test; external testing; fault coverage; function logic; hybrid BIST architecture; hybrid method; test cost reduction; test data compression; tester bandwidth requirements; tester storage requirements; weight set compression; weight set storage; weighted pseudorandom testing; Automatic testing; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Test data compression; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.837985
  • Filename
    1407947