Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.