Low pinch-off voltage amorphous silicon junction field-effect transistor: experiment and simulation

In this work, a junction field effect transistor (JFET) based on a-Si:H is presented. The drain-source contacts are made on top of the n-layer of a glass/metal/p⁺-i-n structure. The channel conductivity can be modulated by a reverse bias applied to the p⁺-i-n junction, which varies the depth or the length of the depletion region. In amorphous silicon, the depletion of doped layers is limited by the high defect density induced by the doping process. Here, the electron concentration of the n-doped layer (the device channel) in a p-i-n amorphous silicon junction is studied by using a one-dimensional finite-difference simulator. The n-channel conductivity is then obtained by integrating the free electron concentration along the drain-source direction. Pinch-off regime is achieved when the n-layer is fully depleted. A JFET with W/L = 400 μm/40 μm was fabricated. Transistors with pinch-off voltages around -3.6 V and transconductance values of the order of 10^-7 A/V were obtained. Comparison between experimental and modeled output characteristics suggests the presence of a defect-rich layer at the channel-air interface. This is related to the damage induced by the process steps during the device fabrication. The achieved experimental results make the device suitable for applications in linear circuits. In particular, unlike thin film transistors (TFTs), JFETs do not require high-temperature, high-quality dielectric layers, and appear particularly attractive for process on plastic substrates.