• DocumentCode
    745495
  • Title

    ThunderBird: a complete standard cell layout package

  • Author

    Sechen, Carl ; Braun, Douglas ; Sangiovanni-Vincentelli, Alberto

  • Author_Institution
    Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
  • Volume
    23
  • Issue
    2
  • fYear
    1988
  • fDate
    4/1/1988 12:00:00 AM
  • Firstpage
    410
  • Lastpage
    420
  • Abstract
    The generalized standard cell layout style handled by ThunderBird is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. The standard cells are permitted to have varying heights. The two key components of ThunderBird are TimberWolf3.2, a standard cell placement and global routing package, and the YACR II channel router. The placement and global routing proceed over three distinct stages: (1) cell placement for minimum interconnect length, (2) insertion of feedthrough cells or location of built-in feeds, and another interconnect-length minimization; and (3) local changes in placement to reduce the number of wiring tracks required. This channel router features a 100% routing completion rate while usually routing each channel using a number of tracks equal to a density of the channel. Results on industrial circuits versus numerous automatic and manual layout methods showed that ThunderBird yielded area savings ranging from 15 to 75%
  • Keywords
    VLSI; cellular arrays; circuit layout CAD; integrated logic circuits; 100% routing completion rate; ThunderBird; TimberWolf3.2; YACR II channel router; area savings; channel router; complete standard cell layout package; generalized standard cell layout style; global routing package; horizontal rows of standard cells; insertion of feedthrough cells; interconnect-length minimization; local changes in placement; macro blocks; pads; placement for minimum interconnect length; varying heights; Algorithm design and analysis; Feeds; Helium; Integrated circuit interconnections; Libraries; Minimization; Packaging; Routing; Simulated annealing; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.1001
  • Filename
    1001