DocumentCode
745517
Title
64-bit reconfigurable adder for low power media processing
Author
Perri, S. ; Corsonello, P. ; Cocorullo, G.
Author_Institution
Dept. of Electron., Comput. Sci. & Syst., Calabria Univ., Italy
Volume
38
Issue
9
fYear
2002
fDate
4/25/2002 12:00:00 AM
Firstpage
397
Lastpage
399
Abstract
A new, highly reconfigurable carry-skip adder for media signal processing is presented. The proposed circuit can be partitioned to perform one 64-, two 32-, four 16- and eight 8-bit additions. Partitioning is obtained without increasing the critical path. When the AMS 0.35 μm two-poly three-metal 3.3 V CMOS (CSD) process is used to produce the layout, the worst propagation delay and dissipation obtained is about 6.5 ns and 148 μW/ MHz
Keywords
CMOS logic circuits; adders; carry logic; delays; integrated circuit layout; integrated circuit measurement; logic partitioning; low-power electronics; reconfigurable architectures; 0.35 micron; 16 bit; 3.3 V; 32 bit; 6.5 ns; 64 bit; 8 bit; AMS two-poly three-metal CMOS process; circuit layout; circuit partitioning; critical path; low power media processing; media signal processing; power dissipation; propagation delay; reconfigurable adder; reconfigurable carry-skip adder;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020295
Filename
1001534
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