Data scheduling scheme for power reduction in DWT-based image coders

Author

Seth, K. ; Srinivasan, S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India

Volume

38

Issue

9

fYear

2002

fDate

4/25/2002 12:00:00 AM

Firstpage

408

Lastpage

409

Abstract

A new memory data scheduling scheme is used for designing a two-dimensional discrete wavelet transform (2D-DWT) core for ASIC implementation. This scheme reduces by 20 to 30% the overall switching activity in the 2D-DWT core and hence leads to lower power consumption at the expense of a slight reduction in the quality of reconstructed images and a slight increase in the chip area. This scheme is particularly useful in applications such as wireless Internet and laptop computers, in which picture quality can be traded-off for reduced power consumption

Keywords

Internet; application specific integrated circuits; discrete wavelet transforms; image coding; image processing equipment; image reconstruction; laptop computers; mobile radio; processor scheduling; 2D discrete wavelet transform core; 2D-DWT core; ASIC implementation; DWT-based image coders; chip area; data scheduling scheme; laptop computers; memory data scheduling scheme; overall switching activity; picture quality; power consumption; power reduction; reconstructed image quality; wireless Internet applications;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20020291

Filename

1001541