Title :
A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS
Author :
Dörrer, Lukas ; Kuttner, Franz ; Greco, Patrizia ; Torta, Patrick ; Hartig, Thomas
Author_Institution :
Infineon Technol. Austria, Villach, Austria
Abstract :
A third-order continuous-time multibit (4 bit) ΔΣ ADC for wireless applications is implemented in a 0.13-μm CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); continuous time filters; delta-sigma modulation; 0.13 micron; 1.5 V; 104 MHz; 2 MHz; 3 mW; 74 dB; CMOS process; DEM technique; capacitive feedforward filter design; continuous-time delta-sigma ADC; digital receiver; dynamic element matching; flash quantizer; jitter tolerant; loop stability; multibit delta-sigma ADC; third-order continuous-time ADC; tracking ADC quantizer; wireless application; 3G mobile communication; Bandwidth; CMOS process; Clocks; Energy consumption; Finite impulse response filter; Interpolation; Jitter; Signal resolution; Stability; Capacitive feedforward filter design; UMTS; continuous-time delta-sigma ADC; digital receiver; dynamic element matching; jitter tolerant; low power; multibit delta-sigma ADC; scrambling; tracking ADC;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.856282