Recursive bitstream conversion: third-order structures

Presents a stability analysis of third-order recursive bitstream converters. It also unifies the algorithm-based concept of recursive bitstream conversion with the structure-based concept of reduced sample-rate sigma-delta modulation. These concepts can both be viewed as generalized sigma-delta modulation with the attractive property that the clock rate within the loop is an "integer fraction" of the bitstream rate as a result of the out-of-loop position of the parallel-to-series or series-to-parallel converter. Both the conversion from a low-sample rate, high-precision signal format to the bitstream format and its inverse have been analyzed. The results of the analyses are demonstrated on a design study of a transceiver for ANSI HDSL2. The developed theory can easily be applied to fourth-order and higher-order structures as well