Title :
Solving satisfiability in combinational circuits
Author :
Marques-Silva, João ; E Silva, Luís Guerra
Author_Institution :
Tech. Univ. Lisbon, Portugal
Abstract :
As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.
Keywords :
Boolean functions; combinational circuits; computability; electronic design automation; field programmable gate arrays; Boolean satisfiability; FPGA; SAT algorithms; combinational circuits; design verification; electronic design automation; Algorithm design and analysis; Boolean functions; Business continuity; Circuit synthesis; Circuit testing; Combinational circuits; Electronic design automation and methodology; Logic design; Logic testing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1214348
