Title :
Power-conscious test synthesis and scheduling
Author :
Nicolici, Nicola ; Al-Hashimi, Bashir M.
Author_Institution :
McMaster Univ., Hamilton, Ont., Canada
Abstract :
BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.
Keywords :
VLSI; built-in self test; integrated circuit testing; scheduling; BIST; VLSI; built in self test; data path circuits; module selection; power dissipation; power-conscious test synthesis; test scheduling; Built-in self-test; Circuit synthesis; Circuit testing; Job shop scheduling; Minimization; Power dissipation; Processor scheduling; Signal processing algorithms; System testing; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1214352
