• DocumentCode
    746512
  • Title

    Power-conscious test synthesis and scheduling

  • Author

    Nicolici, Nicola ; Al-Hashimi, Bashir M.

  • Author_Institution
    McMaster Univ., Hamilton, Ont., Canada
  • Volume
    20
  • Issue
    4
  • fYear
    2003
  • Firstpage
    48
  • Lastpage
    55
  • Abstract
    BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.
  • Keywords
    VLSI; built-in self test; integrated circuit testing; scheduling; BIST; VLSI; built in self test; data path circuits; module selection; power dissipation; power-conscious test synthesis; test scheduling; Built-in self-test; Circuit synthesis; Circuit testing; Job shop scheduling; Minimization; Power dissipation; Processor scheduling; Signal processing algorithms; System testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1214352
  • Filename
    1214352
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=746512