Title :
Test generation for data-path logic: the F-path method
Author_Institution :
David Sarnoff Res. Center Inc., Princeton, NJ, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
Tests for data-path logic can be generated with the aid of high-level methods that utilize the presence of special forms of sensitized paths. These paths, called fault paths (F-paths), are defined so that they transmit fault information with certainty. Their presence can be determined from the functional definition of a block, and when, exceptionally, they are absent, a minimum hardware addition usually suffices to provide them. They permit use of powerful, computer-aided test generation methods that have permitted routine targeting of 100% coverage of an expanded fault set (more than just stuck-ats), verification of success by simple postprocessing of RTL (resistor-transistor logic)-level good-logic simulation
Keywords :
VLSI; integrated circuit testing; integrated logic circuits; logic testing; 100% coverage; F-path method; computer-aided test generation methods; data-path logic; expanded fault set; fault paths; forms of sensitized paths; good-logic simulation; high-level methods; logic test generation; test generation; transmit fault information with certainty; Circuit analysis; Circuit faults; Circuit testing; Computational modeling; Computer simulation; Design for testability; Hardware; Helium; Logic testing; Power generation;
Journal_Title :
Solid-State Circuits, IEEE Journal of