Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of sigma = 0.25% in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).