The modified structure of the lateral IGBT on the SOI wafer for improving the dynamic latch-up characteristics

Author

Sumida, Hitoshi ; Hirabayashi, Atsuo ; Kumagai, Naoki

Author_Institution

Adv. Device Technol. Lab., Fuji Electr. Corp. Res. & Dev. Ltd., Matsumoto, Japan

Volume

42

Issue

2

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

367

Lastpage

370

Abstract

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p⁺-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125°C for the modified LIGBT were 350 A/cm² and 290 A/cm², respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125°C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop

Keywords

equivalent circuits; insulated gate bipolar transistors; power transistors; semiconductor device models; silicon-on-insulator; simulation; 20 to 125 C; LIGBT; SOI wafer; Si; dynamic latchup characteristics; forward voltage drop; inductive load; lateral IGBT; modified structure; numerical simulation; p⁺-emitter layer; turnoff transient; Conductivity; Current density; Equivalent circuits; Impedance; Insulated gate bipolar transistors; Lead; Numerical simulation; Power integrated circuits; Research and development; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.370052

Filename

370052