The study of hot-carrier stress on poly-Si TFT employing C-V measurement

The degradation of n-type and p-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) due to hot-carrier stress was investigated by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide of TFTs are not affected by a small-applied signal, whereas the trap states in the bandgap respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. The capacitance (C_GS) between the source and the gate, as well as the capacitance (C_GD) between the drain and the gate, were measured. The difference between the C_GD and the C_GS indicates the location of degradation in the TFT. Our experimental results showed that the degradation of n-type TFTs was caused by additional trap states in the grain boundary, whereas the degradation of p-type TFTs was caused by electron trapping into the gate oxide.