New Non-Volatile Memory Structures for FPGA Architectures

Author

Choi, David ; Choi, Kyu ; Villasenor, John D.

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA

Volume

16

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

874

Lastpage

881

Abstract

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.

Keywords

CMOS logic circuits; SRAM chips; field programmable gate arrays; flip-flops; switches; transistors; CMOS logic process; FPGA architectures; field-programmable gate array; logical elements; nonvolatile device; nonvolatile flip-flop; nonvolatile memory structures; programmable elements; programmable logic devices; routing switches; thin-oxide pass transistors; CMOS logic circuits; CMOS process; Field programmable gate arrays; Flip-flops; Logic devices; Low voltage; Nonvolatile memory; Programmable logic arrays; Routing; Switches; Field-programmable gate arrays (FPGAs); non-volatile memory;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2000461

Filename

4539803