Universal shift matrix

Serial shifting techniques are slow whereas a totally parallel approach, though fast, is impractical for implementational reasons. A novel intermediate approach is presented whereby circular shifting is performed over two or three levels depending on the factorisation of the shift length n. The use of read-only memories to control its operation and to provide arithmetic and logical shifting produces a hardware structure which can be automatically generated by software for use in cell-based integrated circuit design. This implementation is compared for CMOS and bipolar differential mode logic.