• DocumentCode
    747550
  • Title

    Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

  • Author

    Zhu, Jiangli ; Zhang, Xinmiao ; Wang, Zhongfeng

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA
  • Volume
    17
  • Issue
    11
  • fYear
    2009
  • Firstpage
    1602
  • Lastpage
    1615
  • Abstract
    Recently developed algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes have attracted much interest due to the fact that they can achieve significant coding gain with polynomial complexity. One major step of ASD decoding is the interpolation. Available interpolation algorithms can only add interpolation points or increase interpolation multiplicities. However, backward interpolation, which eliminates interpolation points or reduces interpolation multiplicities, is indispensable to enable the reusing of interpolation results in the following two scenarios: 1) interpolation needs to be carried out on multiple test vectors, which share common entries and 2) iterative ASD decoding where interpolation points have decreasing multiplicities. Examples for these cases are the low-complexity chase (LCC) decoding and bit-level generalized minimum distance (BGMD) decoding. With lower complexity, these algorithms can achieve similar or higher coding gain than other practical ASD algorithms. In this paper, we propose novel backward interpolation schemes and corresponding efficient implementation architectures for LCC and BGMD decoding through constructing equivalent GrOumlbner bases. The proposed architectures share computational units with forward interpolation architectures. Hence, the area overhead for incorporating the backward interpolation is very small. Substantial area saving or speedup can be achieved by using the backward interpolation. When the proposed architecture is applied to the LCC decoding of a (255, 239) RS code with eta = 3, the area is reduced to 39% of those required by prior architectures. In terms of speed/area ratio, the proposed architecture is 48% more efficient than the best available architecture. For the BGMD decoding of the same code, the proposed architecture can achieve around 20% higher efficiency.
  • Keywords
    Reed-Solomon codes; computational complexity; decoding; interpolation; GrOumlbner bases; algebraic soft-decision Reed-Solomon decoding; backward interpolation architecture; bit-level generalized minimum distance decoding; low-complexity chase decoding; polynomial complexity; Backward interpolation; Reed–Solomon (RS) codes; VLSI architecture; bit-level generalized minimum distance (BGMD) decoding; low-complexity Chase (LCC); soft-decision decoding;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2008.2005575
  • Filename
    4837873