DocumentCode :
748748
Title :
On the use of model checking for the verification of a dynamic signature monitoring approach
Author :
Nicolescu, Bogdan ; Gorse, Nicolas ; Savaria, Yvon ; Aboulhamid, El Mostapha ; Velazco, Raoul
Author_Institution :
Ecole Polytechnique de Montreal, Que., Canada
Volume :
52
Issue :
5
fYear :
2005
Firstpage :
1555
Lastpage :
1561
Abstract :
Consequences of transient faults represent a significant problem for today´s electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is mandatory. It is well known that traditional techniques that validate system´s reliability do not cover the whole spectrum of fault scenarios, because fault models are linked to target architectures. Therefore, validating the completeness of robust fault tolerance techniques is a major issue when assessing reliability improvements these techniques can produce. In this paper, we propose an original approach to evaluate the system reliability with respect to Single Event Upset (SEU) errors. It is based on model-checking principles. In addition, a signature analysis technique is evaluated. This technique was previously validated using a simulation-based fault injection approach. Simulation results showed that no error escapes detection. However, simulation based fault injection cannot guarantee that all fault consequences have been investigated. This limitation motivates us to explore a formal verification approach that targets a complete validation. Model checking has a fundamental advantage over classic fault-injection techniques: it can cover all possible SEU fault scenarios from a predefined class. Results reported in this paper demonstrate the efficiency of this validation approach over usual simulation-based techniques.
Keywords :
digital signatures; error correction codes; error detection codes; fault tolerance; formal verification; SEU fault scenarios; electronic circuits; error correction mechanisms; error detection mechanisms; formal verification; model checking; reliability improvements; robust fault tolerance techniques; signature analysis technique; simulation-based fault injection approach; single event upset errors; transient faults; Circuit faults; Electronic circuits; Error correction; Error correction codes; Fault tolerance; Formal verification; Hardware; Monitoring; Single event upset; Very large scale integration; Fault injection; formal verification; model checking; signature analysis;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2005.855819
Filename :
1546458
Link To Document :
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