A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm

Author

Lee, Wen-Ta ; Chan, Ming-Hwa ; Chen, Liang-Gee ; Lin, Mao-Chao

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

41

Issue

1

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

150

Lastpage

159

Abstract

By using an adaptive algorithm, we design a single-chip Viterbi decoder for a rate 1/2 binary convolutional code. The adaptive algorithm is realized by threshold checking at each stage. The survivor paths that are less likely are ignored and hence the number of states at each decoding stage to be computed is reduced significantly in comparison with the conventional Viterbi decoder. Therefore, the decoding speed can be increased. A single-chip hard-decision decoder for a rate 1/2 convolutional code with constraint length K=6 (64 states) has been fabricated in 1.2 μm CMOS technology. Experimental results show that this improved algorithm can achieve a data throughput rate about 3 times faster than that using a conventional algorithm without sacrificing the decoding reliability

Keywords

CMOS digital integrated circuits; Viterbi decoding; adaptive signal processing; binary sequences; convolutional codes; 1.2 μm CMOS technology; 1.2 micron; adaptive algorithm; binary convolutional code; constraint length; data throughput rate; decoding reliability; decoding speed; experimental results; rate 1/2 code; single-chip Viterbi decoder; single-chip hard-decision decoder; threshold checking; Adaptive algorithm; Algorithm design and analysis; CMOS technology; Code standards; Convolutional codes; Maximum likelihood decoding; Throughput; Tin; Viterbi algorithm;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.370322

Filename

370322