On correction of multiple design errors

We consider the problem of correcting multiple design errors in combinational circuits and in finite-state machines. The correction method introduced for combinational circuits uses a single error correction scheme iteratively to correct multiple errors. It uses a heuristic measure that guides the selection of single, local circuit modifications that reduce the distance between the incorrect implementation and the specification. The distance is measured by the size of a correction hardware, which is a block of logic that can be added to the implementation in order to correct it without performing additional circuit modifications. The correction method for finite-state machines is based on the use of pairwise distinguishing sequences for specification and implementation states, and employs the same hardware correction scheme. Experimental results are presented to support the effectiveness of the proposed methods