Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND (OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area