Title :
Optimization by iterative improvement: an experimental evaluation on two-way partitioning
Author :
Yeh, Ching-Wei ; Cheng, Chung-Kuan ; Lin, Ting-Ting Y.
Author_Institution :
Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Taiwan, China
fDate :
2/1/1995 12:00:00 AM
Abstract :
Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 runs are necessary to demonstrate the performance of the Fiduccia-Mattheyses algorithm, whereas traditional way of evaluation tends to underestimate. Nevertheless, our new results show that for two-way partitioning on real circuits, the primal-dual algorithm is, in general, a better choice than both the Fiduccia-Mattheyses algorithm and the simulated annealing algorithm. This conclusion is more likely to hold when the primal-dual algorithm is switched to a simpler mode
Keywords :
circuit CAD; circuit optimisation; integrated circuit design; iterative methods; signal flow graphs; simulated annealing; Fiduccia-Mattheyses algorithm; Kernighan-Lin algorithms; design automation; geometric graphs; iterative improvement; primal-dual algorithm; random graphs; signal flows; simulated annealing; two-way partitioning; Circuit simulation; Circuit testing; Computer science; Feedback circuits; Geometry; Iterative algorithms; Joining processes; Partitioning algorithms; Signal design; Simulated annealing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on