• DocumentCode
    749552
  • Title

    Three-level logic minimization based on function regularities

  • Author

    Bernasconi, Anna ; Ciriani, Valentina ; Luccio, Fabrizio ; Pagli, Linda

  • Author_Institution
    Dipt. di Informatica, Univ. di Pisa, Italy
  • Volume
    22
  • Issue
    8
  • fYear
    2003
  • Firstpage
    1005
  • Lastpage
    1016
  • Abstract
    We exploit the "regularity" of Boolean functions with the purpose of decreasing the time for constructing minimal three-level expressions, in the sum of pseudoproducts (SPP) form recently developed. The regularity of a Boolean function f of n variables can be expressed by an autosymmetry degree k (with 0 ≤ k ≤ n). k = 0 means no regularity, that is we are not able to provide any advantage over standard synthesis. For k ≥ 1 the function f is said to be autosymmetric, and a new function fk depending on n - k variables only, called the restriction of f, is identified in time polynomial in the number of points of f. The relation between f and fk is discussed in depth to show how a minimal SPP form for f can be build in linear time from a minimal SPP form for fk. The concept of autosymmetry is then extended to functions with don\´t care conditions, and the SPP minimization technique is duly extended to such functions. A large set of experimental results is presented, showing that 61% of the outputs for the functions in the classical ESPRESSO benchmark suite are autosymmetric. The minimization time for such functions is critically reduced, and cases otherwise intractable are solved. The quality of the corresponding circuits, measured with some well established cost functions, is also improved. Finally, we discuss the role and meaning of autosymmetric functions, and why a great amount of functions of practical interest fall in this class.
  • Keywords
    Boolean functions; circuit optimisation; logic CAD; minimisation of switching nets; multivalued logic; polynomials; Boolean functions; ESPRFSSO benchmark suite; SPP minimization technique; autosymmetry degree; don´t care conditions; function regularities; minimal three-level expressions; regularity; sum of pseudoproducts; three-level logic minimization; time polynomial; Arithmetic; Boolean functions; Circuit synthesis; Cost function; Design optimization; Helium; Logic circuits; Logic design; Minimization methods; Polynomials;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.814950
  • Filename
    1214859