Title :
PROPTEST: a property-based test generator for synchronous sequential circuits
Author :
Guo, Ruifeng ; Reddy, Sudhakar M. ; Pomeranz, Irith
Author_Institution :
Diagnosis Technol. Dept., Intel Corp., Hillsboro, OR, USA
Abstract :
We describe a property-based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences that achieve high fault coverages at low computational complexity. These include the use of static test compaction, input vector holding with optimal numbers of hold cycles, input vector perturbation, and identification of subsequences that are useful in extending the test sequence. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures.
Keywords :
VLSI; automatic test pattern generation; circuit analysis computing; fault simulation; integrated circuit testing; integrated logic circuits; logic simulation; logic testing; sequential circuits; ATPG; PROPTEST; high fault coverages; input vector holding; input vector perturbation; low computational complexity; property-based test generator; static test compaction; subsequences identification; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Genetics; Logic testing; Sequential analysis; Sequential circuits; Synchronous generators; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.814953
