Title :
Theorems for identifying undetectable faults in partial-scan circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We provide a definition of undetectable faults in partial-scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.
Keywords :
circuit analysis computing; fault diagnosis; finite state machines; identification; logic arrays; sequential circuits; FSM benchmarks; finite-state machine benchmarks; pairwise distinguishing sequences; partial-scan circuits; primary input vectors; scan operations; test application scheme; undetectable faults; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Fault diagnosis; Flip-flops; Logic arrays; Logic circuits; Sufficient conditions;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.814957
