The effect of circuit topology on radiation-induced latchup

Topological factors that affect latchup were investigated using test structures fabricated in two different CMOS foundries. The geometry of isolation well contacts was found to have a large effect on photocurrent responses because of the effect of the lateral resistance of the well. Experiments that delayed the application of bias until time periods long after the radiation pulse subsided showed that latchup would still occur, with relatively small increases in the radiation intensity required to induce latchup until the delays exceeded several microseconds. This shows that the fast transition of the radiation pulse is not required to trigger latchup, and it also shows how latchup can occur at high intensities after internal voltages collapse to near zero at short times. Latchup tests of a 64K SRAM (static random-access memory) revealed a latchup window that was caused by the presence of two different internal latchup paths with different radiation triggering levels and holding voltages. Data on this device and several MSI devices show how the power-supply current-surge characteristics can be used to select radiation test levels to minimize interference from latchup windows