A novel active area bumped flip chip technology for convergent heat transfer from gallium arsenide power devices

Superior low noise amplification characteristics have made gallium arsenide power amplifiers attractive for consumer electronics applications, e.g., cellular phones. To reduce the cost of their introduction, many new technical approaches are being pursued in the areas of device design, fabrication, and even packaging. The difficulty in dissipating heat from conventionally die bonded/wire bonded gallium arsenide power amplifiers forces thinning of finished wafers. There are both yield and environmental issues associated with this operation. A novel lead-free bump technology for active area flip chip bonding of GaAs power amplifiers has been developed (patent pending) in which the heat transfer path from the hot zones in the active area of the device to the heat sink has been shrunk, and the bulk of the GaAs itself has been bypassed. Bumped amplifier flip chips bonded to aluminum nitride substrates can dissipate heat fluxes up to 300 W/cm² with an acceptable rise in junction temperature. By employing this active area bump technology, the junction to substrate thermal resistance has been kept equal to or lower than the conventional wire bond/die bond route using wafer thinning. Therefore, the requirement for thinning of finished wafers can now be eliminated. In order to optimize bump design with respect to bondability and thermal resistance, bumps of various aspect ratios and pitch were plated on the active areas of the power amplifier wafers. Bump profiles of hourglass shape compliant to substrate nonplanarity as well as conducive to improved joint reliability were deposited. Ideal bump geometries were also selected based on the ability of available plating processes to produce bondable bumps. Several flip chip bonding techniques (gold-gold thermosonic as well as gold-tin eutectic) were developed for these active area bumps and evaluated with respect to bendability and bond thermal resistance. Some examples will be provided to illustrate the effects of bonding variables, e.g., chip and substrate temperatures, load and pulse strength on the bonds, and device active area for each of these bonding methods. These data were obtained by metallurgical analyses as well as thermal resistance measurements under dc bias