CMOS phase detector and four quadrant multiplier for implementation in analogue neural networks

Two analogue CMOS circuits for implementation in artificial neural networks are proposed. The phase detector is based on the nonsaturation region of operation of MOS transistors, and the multiplier on the square law characteristics of MOS devices. The multiplier accepts a pair of differential input voltages and can either generate a differential or a single-ended output. It has a measured linearity error of less than 0.5% for an X⁺ input pattern of 2.4 and 2.6 V. The phase detector maintains a phase error of less than 0.1%.