Performance evaluation of the Cray X1 distributed shared-memory architecture

The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1´s distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer´s distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. In this article, we characterize the performance of the X1´s distributed shared-memory system and its interconnection network using microbench-marks and applications.