Performance evaluation of the Cray X1 distributed shared-memory architecture

Author

Dunigan, Thomas H., Jr. ; Vetter, Jeffrey S. ; White, James B., III ; Worley, Patrick H.

Author_Institution

Oak Ridge Nat. Lab., TN, USA

Volume

25

Issue

1

fYear

2005

Firstpage

30

Lastpage

40

Abstract

The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1´s distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer´s distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. In this article, we characterize the performance of the X1´s distributed shared-memory system and its interconnection network using microbench-marks and applications.

Keywords

Cray computers; benchmark testing; distributed shared memory systems; multiprocessor interconnection networks; parallel architectures; parallel machines; performance evaluation; vector processor systems; Cray X1 supercomputer; benchmark testing; distributed shared memory architecture; interconnection network; performance evaluation; vector multiprocessors; Application software; Bandwidth; CMOS technology; Hardware; Memory architecture; Multiprocessor interconnection networks; Parallel processing; Parallel programming; Supercomputers; System software;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2005.20

Filename

1411714