A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Author

Wu, Chung-Yu ; Ker, Ming-Dou ; Lee, Chung-Yuan ; Ko, Joe

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan

Volume

27

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

274

Lastpage

280

Abstract

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies

Keywords

CMOS integrated circuits; VLSI; digital integrated circuits; electrostatic discharge; protection; CMOS VLSI; ESD protection circuit; dual parasitic SCR structures; electrostatic discharge; high-speed applications; human-body-mode; input capacitance; machine-mode; onchip protection; testing; trigger voltages; Breakdown voltage; CMOS technology; Capacitance; Circuit synthesis; Circuit testing; Electrostatic discharge; Low voltage; Performance evaluation; Protection; Thyristors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.121548

Filename

121548