• DocumentCode
    75083
  • Title

    A Highly Scalable Single Poly-Silicon Embedded Electrically Erasable Programmable Read Only Memory With Tungsten Control Gate by Full CMOS Process

  • Author

    Chih-Ping Chung ; Kuei-Shu Chang-Liao

  • Author_Institution
    Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    36
  • Issue
    4
  • fYear
    2015
  • fDate
    Apr-15
  • Firstpage
    336
  • Lastpage
    338
  • Abstract
    A highly scalable single poly-silicon multiple time programmable erasable programmable read only memory (EEPROM) with tungsten metallic control gate (W-CG) manufactured by full 0.13 μm-CMOS process is successfully demonstrated in this letter. Since the coupling ratio of conventional EEPROM cell is reduced with decreasing cell size, a smaller size in W-CG cell with a reduced spacing of CG to floating gate (FG) can obtain a higher coupling ratio and increase programming/erasing window owing to its novel lateral metal-insulator-poly coupling structure.
  • Keywords
    CMOS memory circuits; EPROM; elemental semiconductors; insulators; programmable circuits; silicon; CMOS process; EEPROM cell; FG; Si; W-CG cell; floating gate; lateral metal-insulator-polycoupling structure; programming-erasing window; single polysilicon embedded electrically erasable programmable read only memory; size 0.13 mum; tungsten metallic control gate; CMOS process; Couplings; EPROM; Logic gates; Periodic structures; Programming; System-on-chip; EEPROM; Single poly-silicon EEPROM; embedded EEPROM; full CMOS process; metallic control gate; single poly-silicon; tungsten finger coupling;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2015.2404854
  • Filename
    7047219