Title :
A chip-level modeling approach for rail span collapse and survivability analyses
Author :
Mavis, David G. ; Alexander, David R. ; Dinger, Gregory L.
Author_Institution :
Mission Res. Corp., Albuquerque, NM, USA
fDate :
12/1/1989 12:00:00 AM
Abstract :
A general semiautomated analysis technique has been developed for analyzing rail span collapse and survivability of VLSI microcircuits in high-ionizing-dose-rate radiation environments. Hierarchical macrocell modeling permits analyses at the chip level, and interactive graphical postprocessing provides a rapid visualization of voltage, current, and power distributions for a 16K CMOS/SOI SRAM (static random-access memory) and a CMOS/SOS 8-bit multiplier. An efficient method to treat memory arrays and a three-dimensional integration technique for computing sapphire photoconduction from the design layout are presented
Keywords :
CMOS integrated circuits; VLSI; integrated logic circuits; integrated memory circuits; ion beam effects; multiplying circuits; photoconductivity; radiation hardening (electronics); random-access storage; semiconductor device models; semiconductor-insulator boundaries; CMOS SOI 8-bit multiplier; CMOS SOI SRAM; VLSI microcircuits; chip-level modeling; computing sapphire photoconduction; design layout; hierarchical macrocell modelling; high-ionizing-dose-rate radiation environments; interactive graphical postprocessing; memory arrays; rail span collapse; semiautomated analysis technique; static random-access memory; survivability analyses; three-dimensional integration technique; visualization; Layout; Macrocell networks; Photoconductivity; Power distribution; Rails; Random access memory; Semiconductor device modeling; Very large scale integration; Visualization; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
