DocumentCode
750979
Title
High-performance self-routing algorithm for multiprocessor systems with shuffle interconnections
Author
Francalanci, Chiara ; Giacomazzi, Paolo
Author_Institution
Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
Volume
17
Issue
1
fYear
2006
Firstpage
38
Lastpage
50
Abstract
This paper proposes a routing algorithm for the interconnection of multiple processors based on the shortest-path and deflection-routing principles. The routing algorithm, named SPDRA (Shortest Path and Deflection Routing Algorithm), is applied to multiprocessor systems with a single-stage shuffle physical topology. SPDRA is general-purpose, as opposed to the majority of routing algorithms for multiprocessor systems which are optimized for particular traffic patterns generated by a restricted class of parallel algorithms. The general-purpose nature of SPDRA allows perfomance comparisons with a wide class of routing algorithms for multiprocessor systems that, similar to the single-stage shuffle physical topology, have a fixed node-to-processor ratio. The paper compares SPDRA with hypercube algorithms for bidimensional meshes and torus physical topologies, routing algorithms for hierarchical tridimensional tori, and algorithms for routing permutations in shuffle networks, which constitute the most widely accepted approaches for multiprocessor interconnection. SPDRA exhibits a performance advantage for a broad range of network sizes and, in general, the performance advantage grows as the number of processors increases. However, this paper compares the SPDRA algorithm against a limited set of multiprocessor systems and does not demonstrate a general superiority of SPDRA over all systems with a fixed node-to-processor ratio and, especially, with a growing node-to-processor ratio, such as multistage networks.
Keywords
multiprocessor interconnection networks; network routing; parallel algorithms; bidimensional meshes; deflection-routing principles; high-performance self-routing algorithm; hypercube algorithms; multiprocessor systems; multistage networks; node-to-processor ratio; parallel algorithms; shortest-path principles; shuffle interconnections; single-stage shuffle physical topology; Asynchronous transfer mode; Fast Fourier transforms; Hypercubes; Multiprocessing systems; Multiprocessor interconnection; Multiprocessor interconnection networks; Network topology; Parallel algorithms; Routing; Telecommunication traffic; Multiprocessor systems; self routing.; shuffle interconnection;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/TPDS.2006.11
Filename
1549814
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