• DocumentCode
    751177
  • Title

    Hardware preprocessing for the H1-Level 2 neural network trigger upgrade

  • Author

    Prévotet, J.C. ; Denby, B. ; Fent, J. ; Fröchtenicht, W. ; Garda, P. ; Granado, B. ; Haberer, W. ; Grindhammer, G. ; Janauschek, L. ; Kiesling, C. ; Kobler, T. ; Koblitz, B. ; Nellen, G. ; Schmidt, S. ; Tzamariudaki, E. ; Udluft, S.

  • Author_Institution
    Lab. des Instruments et Systemes d´´Ile de France, Paris, France
  • Volume
    49
  • Issue
    2
  • fYear
    2002
  • fDate
    4/1/2002 12:00:00 AM
  • Firstpage
    362
  • Lastpage
    368
  • Abstract
    The H1-Level 2 neural network trigger has been running successfully at Deutsches Elektronen Synchrotron (DESY) for four years. In order to provide increased selectivity at the higher luminosity planned for the HERA upgrade, an improved "intelligent" preprocessing has been devised. This system extracts complementary physics information from the Level 1 trigger stream and furnishes it to the L2 neural network in order to improve its decision. A new preprocessing board (the Data Distribution Board Version 2-DDB2) is currently being designed at the Max Planck Institute for Physics, Munich, Germany, in order to implement the necessary algorithms in fast field programmable gate arrays (FPGA), taking advantage of parallelism and pipelined structures in order to meet the timing requirement of 8 μs. We present the different algorithmic steps and report on the current status of the DDB2 hardware upgrade
  • Keywords
    data acquisition; electron accelerators; field programmable gate arrays; high energy physics instrumentation computing; neural nets; nuclear electronics; readout electronics; storage rings; timing circuits; trigger circuits; 8 mus; DDB2; DESY; Deutsches Elektronen Synchrotron; FPGA; H1-level 2 neural network trigger upgrade; data distribution board version 2; fast field programmable gate arrays; hardware preprocessing; higher luminosity; intelligent preprocessing; pipelined structures; timing; trigger circuits; Algorithm design and analysis; Data mining; Detectors; Field programmable gate arrays; Neural network hardware; Neural networks; Physics; Synchrotrons; Timing; Trigger circuits;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2002.1003738
  • Filename
    1003738