Title :
A 10-b 20-Msample/s analog-to-digital converter
Author :
Lewis, Stephen H. ; Fetterman, H. Scott ; Gross, George F., Jr. ; Ramachandran, R. ; Viswanathan, T.R.
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
fDate :
3/1/1992 12:00:00 AM
Abstract :
A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm2 and dissipates 240 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.9 micron; 10 bit resolution; 240 mW; 5 MHz; A/D convertor; ADC; CMOS technology; fully differential analog circuits; monolithic IC; pipelined nine-stage architecture; Analog circuits; Analog-digital conversion; BiCMOS integrated circuits; CMOS technology; Costs; Distortion; Paper technology; Power dissipation; Signal resolution; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
