An Experimental 560 Mbits/s Repeater with Integrated Circuits

The bandwidth penalty of digital systems is very obvious in the case of transmission over coaxial cables because of the exponential increse of cable attenuation with square root of frequency. From capacity point of view, it is only at very high information rates (> 500 Mbit/s typically) that a digital system might be competitive with an analog system, because the disadvantage of noise accumulation in an analog system ultimately cancels the bandwidth penalty of the digital system. In addition, it is, however, difficult to realize common functions, such as amplification, equalization, regeneration, clock extraction, etc. with electronic components having a frequency range comparable to the frequency range of the information signal, which extends from zero frequency to the microwave range. Besides, the complexity of a regenerative repeater should be kept to a minimum for reliability reasons. It is shown in the paper that with present-day technology a 560 Mbit/s repeater can be constructed, operating in sections of 1.5 km coaxial cable (2.6/9.5 mm). Also, we demonstrate that new technologies exist which may lead to repeaters with a high degree of monolithic integration, even at such a speed, which is important from the reliability viewpoint. The constructed and described repeater is characterized by unconventional and economic design of amplifier/equalizer and clock extractor and by monolithically integrated decision circuits.