An 80-MFLOPS (peak) 64-b microprocessor for parallel computer

Author

Nakano, Hiraku ; Nakajima, Masaitsu ; Nakakura, Yasuhiro ; Yoshida, Tadahiro ; Goi, Yoshiyuki ; Nakai, Yuji ; Segawa, Reiji ; Kishida, Takeshi ; Kadota, Hiroshi

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

27

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

365

Lastpage

372

Abstract

An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8-μm CMOS technology contains 1300 K transistors. The processor also employs a RISC architecture and Harvard-style bus organization. The authors provide an overview of the processor, especially focusing on processor architecture, floating-point hardware, and performance

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; parallel architectures; parallel machines; reduced instruction set computing; 0.8 micron; 25 ns; 64 bit; 80 MFLOPS; CMOS; Harvard-style bus organization; RISC architecture; floating point addition; floating point multiplication; floating-point hardware; microprocessor; overview; parallel computer; performance; processor architecture; superscalar architecture; two instructions simultaneously; CMOS process; CMOS technology; Computer aided instruction; Computer architecture; Concurrent computing; Microprocessors; Pipelines; Reduced instruction set computing; VLIW; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.121559

Filename

121559