Author_Institution :
Bellcore, Morristown, NJ, USA
Abstract :
As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment. Most techniques can be applied equally well to asynchronous logic-indeed phase alignment is easier-but combining dynamic and asynchronous logic is more difficult. Minimum refresh intervals together with race- and hazard-free operation must be guaranteed. An initial chip implementation that combines dynamic and asynchronous logic running at 500 MHz in 2-μm CMOS is described. With the addition of transistor size optimization, simulations show the same circuit running in the same technology at 800 MHz
Keywords :
CMOS integrated circuits; asynchronous sequential logic; integrated logic circuits; logic design; 2 micron; 500 to 800 MHz; chip implementation; dynamic asynchronous logic; dynamic logic; hazard-free operation; high-speed CMOS systems; inverting logic; minimum refresh intervals; phase alignment; race-free operation; redundant logic; self-timed asynchronous logic; transistor size optimization; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Degradation; Design optimization; Logic design; Pulse inverters; Synchronization; System performance;
