Practical delay enforced multistream (DEMUS) control of deeply pipelined processors

The simulated performance of a practical multithreaded mechanism for achieving high utilization of deeply pipelined (>5 stage) processors is presented. Threads are dynamically interleaved in one pipeline. After each instruction is dispatched, enough delay is introduced so that successive instructions cannot interfere. Four scheduling algorithms, three of which are realizable, are tested on a simple simulated processor. Good pipeline utilization can be achieved even when the number of running threads is less than the number of pipeline stages